This post is about my understanding related to how RTEMS initializes SMP.
From start.S first going to bsp_start_hook_0, then arm_a9mpcore_start_hook_0 (in arm_a9mpcore-start.h) , where the secondary cores call the function arm_a9mpcore_start_on_secondary_processor() ,which performs cache, mmu initialization for them. The primary core thread goes on to call boot_card().
After bsp_hooks, starting from boot_card(), I traced some functions for the primary core (of the highly modular code :)) , which I could get hold of for now. Below is a picture to capture the sequence very briefly
Much of SMP work is based on a9mpcore. Parts of the SMP code lead to a9mpcore specific functions in arm-a9mpcore-smp.c and also to bsp specific implementation in bspsmp.c . So what I see is that , to keep this sequence consistent for Pi 2 as well, we will have to provide Pi 2 specific code for these functions instead of using definitions from these files.
There is arm-gic based interrupt handling which will not be relevant to Pi 2 as it simply does not use that interrupt controller.
Next: Starting secondary cores with RTEMS
From start.S first going to bsp_start_hook_0, then arm_a9mpcore_start_hook_0 (in arm_a9mpcore-start.h) , where the secondary cores call the function arm_a9mpcore_start_on_secondary_processor() ,which performs cache, mmu initialization for them. The primary core thread goes on to call boot_card().
After bsp_hooks, starting from boot_card(), I traced some functions for the primary core (of the highly modular code :)) , which I could get hold of for now. Below is a picture to capture the sequence very briefly
Much of SMP work is based on a9mpcore. Parts of the SMP code lead to a9mpcore specific functions in arm-a9mpcore-smp.c and also to bsp specific implementation in bspsmp.c . So what I see is that , to keep this sequence consistent for Pi 2 as well, we will have to provide Pi 2 specific code for these functions instead of using definitions from these files.
There is arm-gic based interrupt handling which will not be relevant to Pi 2 as it simply does not use that interrupt controller.
Next: Starting secondary cores with RTEMS
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